Conventional microprocessors typically include a universal asynchronous receiver transmitter (UART) interface for communicating with other entities. The UART interface uses an oversampling clock that is conventionally 16 times the bit rate such that each received bit is represented by sixteen samples. To send a binary one under the UART transmission protocol, the transmitting UART interface drives its TX pin to the power supply voltage VDD for the duration of the bit period as determined by sixteen cycles of its oversampling clock. The receiving UART interface counts its bit period using its own oversampling clock. Transmission of a logical zero is analogous in that the transmitting UART interface grounds its transmit pin for the duration of the bit period as determined by its oversampling clock (sixteen cycles). The resulting data transmission is in frames of eight bits and may include parity and check-sum bits.
The UART transmission protocol with hardware flow control may be better understood with reference to FIG. 1, which illustrates the UART interfaces for device 1 and a device 2. Each UART interface has four pins or terminals: a transmit pin TX, a receive pin RX, a request to send (RTS) pin, and a clear to send (CTS) pin. The transmit pin for each device couples to the receive pin for the opposing device. Similarly, the RTS pin for each device couples to the CTS pin for the opposing device. Suppose that device 1 is ready to receive data from device 2. It would then assert the voltage on its RTS pin so that the resulting asserted voltage is received on the CTS pin for device 2. Should device 2 have a frame of data to send, it would then send the data frame over its TX pin to be received on the RX pin for device 1. The transmission protocol for transmitting data from device 1 to device 2 is analogous in that device 1 can only send a frame of data if device 2 has asserted a voltage on its RTS pin. The resulting transmission protocol advantageously requires no software intervention or control. Processor(s) in either device are thus relieved of any management burden with regard to the UART data transmission.
Although UART interfaces are simple and relatively robust, an integrated circuit needs to require four pins for their implementation. These extra pins add cost and complexity to the resulting integrated circuit. Accordingly, there is a need in the art for UART interfaces having a reduced number of pins.